1. Field of the Invention
The present invention generally relates to a display apparatus with a drive circuit, and more specifically, to a line inverting drive type display apparatus with a drive circuit in which power consumption can be reduced.
2. Description of the Related Art
A display apparatus such as a liquid crystal display (LCD) apparatus is widely used in various electronic appliances such as mobile communication terminals. A long time operation is required in the display apparatus using a battery. Therefore, power consumption required to drive the display apparatus should be reduced.
As typical liquid crystal display (LCD) drive systems, a line inverting drive system and a frame inverting drive system are well known in the field. In both LCD drive systems, a polarity of voltage applied between electrodes is switched at a timing when a line or a frame is switched. The reason why the switching of polarity of applied voltage is required is given as follows. That is, when a voltage having the same polarity is continuously applied to a LCD cell, a characteristic of the LCD cell is deteriorated.
FIGS. 1A to 1D are timing charts showing electrode drive timing performed in accordance with the line inverting drive system. In the line inverting drive system, the polarity of a voltage applied between a common electrode and a segment electrode is inverted for every scanning line. Similarly, FIGS. 2A to 2C are timing charts showing electrode drive timing in the frame inverting drive system. In the frame inverting drive system, the polarity of a voltage applied between a common electrode and a segment electrode is inverted for every field. In the figures, symbol COMm (symbol xe2x80x9cmxe2x80x9d is an integer) shows the voltage level of the common electrode, and symbol SEGn (symbol xe2x80x9cnxe2x80x9d is an integer) represents the voltage level of the segment electrode. In FIGS. 1A to 1D and FIGS. 2A to 2C, the respective voltage levels are indicated over two frame periods.
Japanese Laid Open Patent Application (JP-A-Heisei 4-67122) describes the technique in which a flicker problem can be eliminated and also a transistor element can be made compact in the LCD element drive system. Also, Japanese Laid Open Patent Application (JP-A-Heisei 8-76083) describes the technique in which a stable operation period can be made long and also a cross-talk can be reduced in the LCD drive apparatus. Furthermore, Japanese Laid Open Patent Application (JP-A-Heisei 9-230829) discloses the technique of a source driver output circuit for driving for a short time in a high power usage efficiency. In addition, Japanese Laid Open Patent Application (JP-A-Heisei 9-236790) describes the technique for reducing a cross-talk in the LCD display device.
FIG. 3 is a block diagram showing a conventional liquid crystal display (LCD) drive circuit of the line inverting drive system. The conventional LCD drive circuit is composed of a power supply circuit 201, a timing generator 203, a common electrode selecting circuit 205, a common signal generating circuit 207, a segment signal generating circuit 209, a first switch unit 211, and a second switch unit 213.
The first switch unit 211 is composed of switch pairs corresponding to common electrodes, respectively. The different voltages are applied to each of switches SWDm and SWEm of each switch pair. The second switch unit 213 is composed of switch pairs corresponding to segment electrodes, respectively. The different voltages are applied to each of switches SWFn and SWGn of each switch pair.
FIGS. 4A to 4F are timing charts of the LCD drive circuit shown in FIG. 3. The timing generator 203 divides a clock signal 215 of FIG. 4A in frequency to produce a frequency-divided clock signal 217, as shown in FIG. 4B. The frequency-divided clock signal 217 specifies line inverting drive timing.
In response to the frequency-divided clock signal 217, the first switch unit 211 and the second switch unit 213 may switch each of the switch pairs. For example, when the common electrode COM1 is selected in a selection period xe2x80x9ct2xe2x80x9d of FIG. 4D, the voltage applied to the common electrode COM1 changes at the line inverting timing xe2x80x9ct1xe2x80x9d, as shown in FIG. 4E. Similar to the common electrode, the voltage applied to the segment electrode is changed. It should be noted that only segment electrode xe2x80x9cSEG1xe2x80x9d is shown in FIG. 4F.
In the liquid crystal display apparatus of the line inverting drive system, the polarity of the voltage applied between the electrodes is inverted for every line. At the timing xe2x80x9ct1xe2x80x9d when the polarity is inverted, charges stored between the electrodes are previously discharged. Also, the power is consumed based on the voltage level required to be inverted.
An object of the present invention is to provide a display apparatus with a drive circuit in which power consumption can be reduced.
Another object of the present invention is to provide a liquid crystal display drive circuit in which power consumption can be reduced at a timing when the polarity of a voltage applied between electrodes is switched.
Still another object of the present invention is to provide a liquid crystal display drive circuit in which power consumption can be reduced by adding a simple circuit.
In order to achieve an aspect of the present invention, a display apparatus includes a display panel and a logic switch unit. The display panel has a plurality of common electrodes and a plurality of segment electrode arranged in a direction orthogonal to the plurality of common electrodes. Display cells are formed at intersections of the plurality of common electrodes and the plurality of segment electrodes. The logic switch unit short-circuits selected ones of the plurality of common electrodes corresponding to a display cell group and selected ones of the plurality of segment electrodes corresponding to the display cell group in response to a common-segment short-circuit timing signal. The display cell group includes selected ones of the display cells.
The logic switch unit preferably short-circuits the selected segment electrodes in response to a segment short-circuit timing signal, before the selected common electrodes and the selected segment electrodes are short-circuited.
Also, a number of the selected common electrodes is 1, and the common-segment short-circuit timing signal is generated before a line inverting operation to the common electrode.
The common-segment short-circuit timing signal is generated such that electric charge stored between the selected common electrode and the selected segment electrodes is redistributed.
It is preferable that the selected common electrode is electrically disconnected from the selected segment electrodes, when the stored charge substantially reaches a preset value.
In order to achieve another aspect of the present invention, a liquid crystal display drive circuit for driving a display panel which has a plurality of common electrodes and a plurality of segment electrode arranged in a direction orthogonal to the plurality of common electrodes. The liquid crystal display drive circuit includes a timing control unit, a common electrode driving unit, a segment electrode drive unit and a logic switch unit. The timing control unit frequency-divides a clock signal to generate a first timing signal and a second timing signal from the frequency-divided clock signal, and inputs a display data to output a segment data corresponding to the plurality of segment electrodes. The common electrode drive unit generates a common selection signal based on the frequency-divided clock signal and the first timing signal to select one of the plurality of common electrodes. Also, the common electrode drive unit generates a common drive signal used to drive the selected common electrode with a selected one of a plurality of first levels. The segment electrode drive unit generates a segment drive signal used to drive each of the plurality of segment electrodes with a selected one of a plurality of second levels. The logic switch unit responds to the common selection signal and the second timing signal to electrically disconnect the selected common electrode from the common drive signal, and to electrically disconnect the plurality of segment electrodes from the segment drive signal. Then, the logic switch unit responds to the common selection signal and the second timing signal to short-circuit the common electrode and the plurality of segment electrodes.
The first timing signal is preferably generated to start a line inverting operation to the selected common electrode, and the second timing signal is preferably generated such that the selected common electrode is short-circuited to the plurality of segment electrodes before the line inverting operation.
The timing control unit may include a frequency dividing unit, a first delay unit and a second timing signal generating unit. The frequency dividing unit frequency-divides the clock signal to generate the frequency-divided clock signal based on a preset value. The first delay unit delays the frequency-divided clock signal based upon a preset time to output the first timing signal. The second timing signal generating unit generates the second timing signal based on the frequency-divided clock signal and the first timing signal such that the second timing signal is activated in synchronous with the frequency-divided clock signal. The first timing signal is generated while the second timing signal is activated.
The segment data are supplied to the segment electrode drive unit in parallel in correspondence with the plurality of segment electrodes.
Also, two different voltage levels may be allocated to the common drive signal for the selected first level, and a voltage level of the common drive signal may be changed in response to a falling timing of the second timing signal. Also, two different voltage levels may be allocated to the segment drive signal for the selected second level, and a voltage level of the segment drive signal may be changed in response to a falling timing of the second timing signal.
The logic switch unit includes a first disconnecting unit, a first short-circuit unit, a disconnect instruction generating unit, a second disconnecting unit and a second short-circuit unit. The first disconnecting unit electrically disconnects the plurality of segment electrodes from the segment drive signal in response to the second timing signal. The first short-circuit unit short-circuits the plurality of segment electrodes to each other in response to the second timing. The disconnect instruction generating unit generates a disconnect instruction based on the second timing signal and the common selection signal. The second disconnecting unit electrically disconnects the selected common electrode from the common drive signal in response to the disconnect instruction. The second short-circuit unit short-circuits the selected common electrode to the plurality of segment electrodes in response to the disconnect instruction.
In order to achieve still another aspect of the present invention, a liquid crystal display drive circuit for driving a display panel which has a plurality of common electrodes and a plurality of segment electrode arranged in a direction orthogonal to the plurality of common electrodes. The liquid crystal display drive circuit includes a timing control unit, a common electrode drive unit, a segment electrode drive unit and a logic switch unit. The timing control unit frequency-divides a clock signal to generate a first timing signal and a second timing signal from the frequency-divided clock signal, and inputs a display data to output a segment data corresponding to each of the plurality of segment electrodes. The common electrode drive unit generates a common selection signal based on the frequency-divided clock signal and the first timing signal to select one of the plurality of common electrodes. Also, the common electrode drive unit generates first and second common drive signals used to alternately drive the selected common electrode with a selected one of a plurality of first levels. The segment electrode drive unit generates a segment drive signal used to drive each of the plurality of segment electrodes with a selected one of a plurality of second levels. The logic switch unit electrically disconnects the selected common electrode from the first and second common drive signals in response to the first and second timing signals. Also, the logic switch unit electrically disconnects the plurality of segment electrodes from the segment drive signal based on the common selection signal and the second timing signal. Then, the logic switch unit short-circuits the selected common electrode and the plurality of segment electrodes.
The first timing signal is preferably generated to start a line inverting operation to the selected common electrode, and the second timing signal is preferably generated such that the selected common electrode is short-circuited to the plurality of segment electrodes before the line inverting operation.
The timing control unit includes a frequency dividing unit, a first delay unit and a second timing signal generating unit. The frequency dividing unit frequency-divides the clock signal to generate the frequency-divided clock signal based on a preset value. The first delay unit delays the frequency-divided clock signal based upon a preset time to output the first timing signal. The second timing signal generating unit generates the second timing signal based on the frequency-divided clock signal and the first timing signal such that the second timing signal is activated in synchronous with the frequency-divided clock signal. The first timing signal is generated while the second timing signal is activated.
The segment data are supplied to the segment electrode drive unit in parallel in correspondence with the plurality of segment electrodes. The first and second common drive signals are alternatively switched based on the first and second timing signals.
Two different voltage levels are preferably allocated to the segment drive signal for the selected second level, and a voltage level of the segment drive signal is preferably changed in response to a falling timing of the second timing signal.
The logic switch unit may include a first disconnecting unit, a first short-circuit unit, a disconnect timing generating unit, a second disconnecting unit and a short-circuit instruction generating unit. The first disconnecting unit electrically disconnects the plurality of segment electrodes from the segment drive signal in response to the second timing signal. The first short-circuit unit short-circuits the plurality of segment electrodes to each other in response to the second timing. The disconnect timing generating unit generates first and second disconnect instructions based on the first and second timing signals. The second disconnecting unit electrically disconnects the selected common electrode from the first and second common drive signals in response to the first and second disconnect instructions. The short-circuit instruction generating unit generates a short-circuit instruction based on the second timing signal and the common selection signal such that the selected common electrode to the plurality of segment electrodes are short-circuited to each other in response to the short-circuit instruction.